This invention is directed to improvements in digital frequency dividers. It is particularly directed to such dividers which are adapted to divide a clock frequency by an odd number.
Many applications require that the frequency of a symmetrical clock signal (fc) be divided by an odd number N to obtain an output fc/N. Although this type of division is relatively easy to accomplish, it is somewhat harder to ensure that the output fc/N is symmetrical. For example, waveform A of FIG. 1 shows a clock signal fc whose frequency is to be divided by five. Most conventional digital dividers produce the unsymmetrical output shown as waveform B of FIG. 1.
To develop a divided output which is symmetrical (waveform C of FIG. 1), it has been proposed to multiply the clock signal fc by two, then divide the multiplied clock signal by five (or any odd number), and then divide the last quotient by two. Although this technique produces a symmetrical output, the circuitry required is relatively complex, and, therefore, expensive.